High-Speed Continuous-Time Subsampling Bandpass ∆Σ AD Modulator Architecture Employing Radio Frequency DAC

This paper proposes a continuous-time bandpass ∆ΣAD modulator architecture which performs high-accuracy AD conversion of high frequency analog signals and can be used for next-generation radio systems. We use an RF DAC inside the modulator to enable subsampling and also to make the SNDR of the continuous-time modulator insensitive to DAC sampling clock jitter. We have confirmed that this is the case by MATLAB simulation. We have also extended our modulator to multi-bit structures and show that this alleviates excess loop delay problems. key words: continuous-time, subsampling, bandpass, ∆Σ modulator, RF DAC, jitter